1/8 october 2001 STU13NC50 n-channel 500v - 0.31 w - 13a max220 powermesh?ii mosfet n typical r ds (on) = 0.31 w n extremely high dv/dt capability n 100% avalanche tested n new high voltage benchmark n gate charge minimized description the powermesh ? ii is the evolution of the first generation of mesh overlay ?. the layout re- finements introduced greatly improve the ron*area figure of merit while keeping the device at the lead- ing edge for what concerns swithing speed, gate charge and ruggedness. applications n high current, high speed switching n uninterruptible power supplies (ups) n dc-ac converters for telecom, industrial, and lighting equipment absolute maximum ratings (?)pulse width limited by safe operating area type v dss r ds(on) i d STU13NC50 500v < 0.4 w 13 a symbol parameter value unit v ds drain-source voltage (v gs = 0) 500 v v dgr drain-gate voltage (r gs = 20 k w ) 500 v v gs gate- source voltage 30 v i d drain current (continuos) at t c = 25c 13 a i d drain current (continuos) at t c = 100c 8a i dm ( l ) drain current (pulsed) 52 a p tot total dissipation at t c = 25c 160 w derating factor 1.28 w/c dv/dt(1) peak diode recovery voltage slope 3.5 v/ns t stg storage temperature C65 to 150 c t j max. operating junction temperature 150 c (1)i sd 13a, di/dt 130a/s, v dd v (br)dss , t j t jmax. 1 2 3 max220 internal schematic diagram
STU13NC50 2/8 thermal data avalanche characteristics electrical characteristics (tcase = 25 c unless otherwise specified) off on (1) dynamic rthj-case thermal resistance junction-case max 0.78 c/w rthj-amb thermal resistance junction-ambient max 62.5 c/w t l maximum lead temperature for soldering purpose 300 c symbol parameter max value unit i ar avalanche current, repetitive or not-repetitive (pulse width limited by t j max) 13 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 800 mj symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 500 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating 1a v ds = max rating, t c = 125 c 50 a i gss gate-body leakage current (v ds = 0) v gs = 30v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 234v r ds(on) static drain-source on resistance v gs = 10v, i d = 7 a 0.31 0.4 w symbol parameter test conditions min. typ. max. unit g fs forward transconductance v ds > i d(on) x r ds(on)max, i d =7a 13 s c iss input capacitance v ds = 25v, f = 1 mhz, v gs = 0 1970 pf c oss output capacitance 300 pf c rss reverse transfer capacitance 48 pf
3/8 STU13NC50 thermal impedance electrical characteristics (continued) switching on switching off source drain diode note: 1. pulsed: pulse duration = 300 s, duty cycle 1.5 %. 2. pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time rise time v dd = 250v, i d = 7 a r g = 4.7 w v gs = 10v (see test circuit, figure 3) 20 ns t r 23 ns q g total gate charge v dd = 400v, i d = 14 a, v gs = 10v 75 105 nc q gs gate-source charge 10 nc q gd gate-drain charge 38 nc symbol parameter test conditions min. typ. max. unit t r(voff) off-voltage rise time v dd = 400v, i d = 14 a, r g = 4.7 w, v gs = 10v (see test circuit, figure 5) 25 ns t f fall time 30 ns t c cross-over time 62 ns symbol parameter test conditions min. typ. max. unit i sd source-drain current 13 a i sdm (2) source-drain current (pulsed) 52 a v sd (1) forward on voltage i sd = 14 a, v gs = 0 1.4 v t rr reverse recovery time i sd = 14 a, di/dt = 100a/s, v dd = 100v, t j = 150c (see test circuit, figure 5) 670 ns q rr reverse recovery charge 6.7 c i rrm reverse recovery current 20 a safe operating area
STU13NC50 4/8 gate charge vs gate-source voltage capacitance variations static drain-source on resistance transfer characteristics output characteristics transconductance
5/8 STU13NC50 normalized gate thereshold voltage vs temperature normalized on resistance vs temperature source-drain diode forward characteristics
STU13NC50 6/8 fig. 5: test circuit for inductive load switching and diode recovery times fig. 4: gate charge test circuit fig. 2: unclamped inductive waveform fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuit for resistive load
7/8 STU13NC50 dim. mm inch min. typ. max. min. typ. max. a 4.3 4.6 0.169 0.181 a1 2.2 2.4 0.087 0.094 a2 2.9 3.1 0.114 0.122 b 0.7 0.93 0.027 0.036 b1 1.25 1.4 0.049 0.055 b2 1.2 1.38 0.047 0.054 c 0.45 0.6 0.18 0.023 d 15.9 16.3 0.626 0.641 d1 9 9.35 0.354 0.368 d2 0.8 1.2 0.031 0.047 d3 2.8 3.2 0.110 0.126 e 2.44 2.64 0.096 0.104 e 10.05 10.35 0.396 0.407 l 13.2 13.6 0.520 0.535 l1 3 3.4 0.118 0.133 a a2 a1 c d3 d1 d2 d b1 b2 b e l l1 e p011r max220 mechanical data
STU13NC50 8/8 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics a 2000 stmicroelectronics - all rights reserved all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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